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CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
3.3V 32K/64K x 16/18 Dual-Port Static RAM
Features

True Dual-Ported memory cells which allow simultaneous access of the same memory location [1] 32K x 16 organization (CY7C027V/027VN/027AV ) 64K x 16 organization (CY7C028V) [2] 32K x 18 organization (CY7C037V/037AV ) 64K x 18 organization (CY7C038V) 0.35 micron CMOS for optimum speed and power High speed access: 15, 20, and 25 ns Low operating power Active: ICC = 115 mA (typical) Standby: ISB3 = 10 A (typical)
Fully asynchronous operation Automatic power down Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flag for port-to-port communication Separate upper-byte and lower-byte control Dual chip enables Pin select for Master or Slave Commercial and Industrial temperature ranges 100-pin Pb-free TQFP and 100-pin TQFP
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
CEL
CER
CE0R CE1R LBR OER
I/O8/9L-I/O15/17L I/O0L-I/O7/8L
[4]
[3]
8/9 8/9
8/9
[3]
I/O Control
I/O Control
8/9
I/O8/9L-I/O15/17R I/O0L-I/O7/8R
[4]
A0L-A14/15L
[5]
15/16
Address Decode
15/16
True Dual-Ported RAM Array
Address Decode
15/16
15/16
A0R-A14/15R
[5]
A0L-A14/15L CEL OEL R/WL SEML BUSYL INTL UBL LBL
[6]
[5]
Interrupt Semaphore Arbitration
A0R-A14/15R CER OER R/WR SEMR
[6]
[5]
M/S
BUSYR INTR UBR LBR
Notes 1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical. 2. CY7C037V and CY7C037AV are functionally identical. 3. I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices. 4. I/O0-I/O7 for x16 devices; I/O0-I/O8 for x18 devices. 5. A0-A14 for 32K; A0-A15 for 64K devices. 6. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation Document #: 38-06078 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 09, 2008
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CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
BUSYR BUSYL INTR GND INTL A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 65 M/S A8L A7L A6L A5L A4L A3L A2L A1L A0L NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [1] A15L NC NC LBL UBL CE0L CE1L SEML VCC R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9R A10R A11R A12R A13R A14R A15R [1] NC NC LBR UBR CE0R CE1R SEMR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
CY7C028V (64K x 16) CY7C027V/027VN/027AV (32K x 16)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O0R
I/O9R
GND
GND
VCC
VCC
I/O3L
I/O2L
I/O1L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
Note 1. This pin is NC for CY7C027V/027VN/027AV.
Document #: 38-06078 Rev. *B
I/O4L
I/O0L
I/01R
NC
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Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
BUSYR BUSYL INTR GND GND INTL
VCC
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [2] A15L LBL UBL CE0L CE1L SEML R/WL OEL VCC GND I/O17L I/O16L GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 A8R A9R A10R A11R A12R A13R A14R A15R [2] LBR UBR CE0R CE1R SEMR R/WR GND OER GND I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
CY7C038V (64K x 18) CY7C037V/037AV (32K x 18)
A7R 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O10R
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
M/S
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
Parameter Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 (Both ports TTL level) Typical Standby Current for ISB3 (Both ports CMOS level) -15 15 125 35 10 A -20 20 120 35 10 A -25 25 115 30 10 A Unit ns mA mA A
Note 2. This pin is NC for CY7C037V/037AV.
Document #: 38-06078 Rev. *B
I/O9R
I/01R
GND
GND
VCC
VCC
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Pin Definitions
Left Port CE0L, CE1L R/WL OEL A0L-A15L I/O0L-I/O17L SEML UBL LBL INTL BUSYL M/S VCC GND NC R/WR OER A0R-A15R I/O0R-I/O17R SEMR UBR LBR INTR BUSYR Right Port CE0R, CE1R Read/Write Enable Output Enable Address (A0-A14 for 32K; A0-A15 for 64K devices) Data Bus Input/Output (I/O0-I/O15 for x16 devices; I/O0-I/O17 for x18) Semaphore Enable Upper Byte Select (I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices) Lower Byte Select (I/O0-I/O7 for x16 devices; I/O0-I/O8 for x18 devices) Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip select (CE) pin. The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Description Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
Architecture
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
Write Operation
Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port.
Functional Description
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or
Read Operation
When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/027VN/027AV/037V/037AV, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is
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generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2.
Busy
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW.
are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore.
Master/Slave
A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores
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CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
DC Input Voltage[2] .................................. -0.5V to VCC+0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 1100V Latch-up Current.................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential................-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ........................... -0.5V to VCC+0.5V
Operating Range
Range Commercial Industrial[3] Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Electrical Characteristics Over the Operating Range
CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Min Output HIGH Voltage (VCC=Min., IOH= -4.0 mA) Output LOW Voltage (VCC=Min., IOH= +4.0 mA) Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current (VCC=Max. IOUT=0 mA) Outputs Disabled Standby Current (Both Ports TTL Level) CEL & CER VIH, f=fMAX Com'l. Ind.[3] Com'l. Ind.[3] 80 10 75 120 250 105 35 50 -5 -10 125 2.2 0.8 5 10 185 -5 -10 120 140 35 45 75 85 10 10 70 80 2.4 0.4 2.2 0.8 5 10 175 195 45 55 110 120 250 250 95 105 60 80 10 250 65 95 30 40 -5 -10 115 -15 Typ Max Min 2.4 0.4 2.2 0.8 5 10 165 -20 Typ Max Min 2.4 0.4 -25 Typ Max V V V V A A mA mA mA mA mA mA A A mA mA Unit
Standby Current (One Port TTL Level) Com'l. CEL | CER VIH, f=fMAX Ind.[3] Standby Current (Both Ports CMOS Level) CEL & CER VCC-0.2V, f=0 Com'l. Ind.
[3]
Standby Current (One Port CMOS Lev- Com'l. el) CEL | CER VIH, f=fMAX[4] Ind.[3]
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 10 10 Unit pF pF
Notes 2. Pulse width < 20 ns. 3. Industrial parts are available in CY7C028V and CY7C038V only. 4. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 5. Tested initially and after any design or process changes that may affect these parameters.
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Figure 3. AC Test Loads and Waveforms
3.3V 3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4V OUTPUT C = 30 pF RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1) ALL INPUT PULSES
3.0V GND 10% 3 ns 90% 90% 10% 3 ns
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig)
Switching Characteristics
Parameter
Over the Operating Range[6] CY7C027V/027VN/027AV/028V/ CY7C037V/037AV/038V
Description Min
-15 Max Min 20 15 3 15 10 3 10 3 10 0 15 15 15 12 12 0 0 12 10 20 16 16 0 0 17 12 0 3 3 3
-20 Max Min 25 20 3 20 12 3 12 3 12 0 20 20 25 20 20 0 0 22 15
-25 Max
Unit
Read Cycle tRC tAA tOHA tACE[7] tDOE tLZOE[8, 9, 10] tHZOE[8, 9, 10] tLZCE[8, 9, 10] tHZCE[8, 9, 10] tPU[10] tPD[10] tABE[7] Write Cycle tWC tSCE[7] tAW tHA tSA[7] tPWE tSD Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Setup to Write Start Write Pulse Width Data Setup to Write End ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power Up CE HIGH to Power Down Byte Enable Access Time 15 ns 25 25 13 15 15 25 25 ns ns ns ns ns ns ns ns ns ns ns
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 7. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 9. Test conditions used are Load 2. 10. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.
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Switching Characteristics Over the Operating Range[6](continued)
CY7C027V/027VN/027AV/028V/ CY7C037V/037AV/038V Parameter Description Min tHD tHZWE[9, 10] tLZWE[9 ,10] tWDD[36] tDDD[36] Busy Timing[11] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[13] tINS tINR tSOP tSWRD tSPS tSAA BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid
[11]
-15 Max 10 3 30 25 15 15 15 15 5 0 13 15 15 15 10 5 5 15 10 5 5 5 0 15 3 Min 0 0
-20 Max 12 3 40 30 20 20 20 16 5 0 17 20 20 20 12 5 5 20 Min 0
-25 Max
Unit
Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
ns 15 50 35 20 20 20 17 ns ns ns ns ns ns ns ns ns ns ns 25 20 20 ns ns ns ns ns ns 25 ns
Interrupt Timing
INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time
Semaphore Timing
Data Retention Mode
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between VCC - 0.2V and 70% of VCC during the power up and power down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts).
Timing
Data Retention Mode VCC 3.0V VCC > 2.0V 3.0V tRC
V IH
CE
VCC to VCC - 0.2V
Parameter ICCDR1
Test Conditions[14] At VCCDR = 2V
Max 50
Unit A
Notes 11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform. 12. Test conditions used are Load 1. 13. tBDD is a calculated parameter and is the greater of tWDD-tPWE (actual) or tDDD-tSD (actual). 14. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.
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Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access)[15, 16, 17]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA
PREVIOUS DATA VALID
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[15, 18, 19]
CE and LB or UB OE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID tACE tHZCE tDOE tHZOE
Figure 6. Read Cycle No. 3 (Either Port)[15, 17, 18, 19]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
Notes 15. R/W is HIGH for read cycles. 16. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 17. OE = VIL. 18. Address valid prior to or coincident with CE transition LOW. 19. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
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Switching Waveforms(continued)
Figure 7. Write Cycle No. 1: R/W Controlled Timing[20, 21, 22, 23]
tWC ADDRESS tHZOE [26] OE tAW CE
[24,25]
tSA R/W tHZWE[26] DATA OUT NOTE 27
tPWE[23]
tHA
tLZWE NOTE 27 tSD tHD
DATA IN
Figure 8. Write Cycle No. 2: CE Controlled Timing[20, 21, 22, 28]
tWC ADDRESS tAW CE
[24,25]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Notes 20. R/W must be HIGH during all address transitions. 21. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 22. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 24. To access RAM, CE = VIL, SEM = VIH. 25. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 26. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 27. During this period, the I/O pins are in the output state, and input signals must not be applied. 28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
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Switching Waveforms(continued)
Figure 9. Semaphore Read After Write Timing, Either Side[29]
tSAA tOHA
A0-A 2
VALID ADRESS tAW
VALID ADRESS tACE tSOP
SEM tSCE tSD I/O 0 tSA R/W
tHA
DATAIN VALID tPWE tHD
DATAOUT VALID
tSWRD OE WRITE CYCLE tSOP
tDOE
READ CYCLE
Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]
A0L -A2L
MATCH
R/WL SEM L tSPS A 0R -A 2R MATCH
R/WR SEM R
Notes 29. CE = HIGH for the duration of the above timing (both write and read cycle). 30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 31. Semaphores are reset (available to both ports) at cycle start. 32. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
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Switching Waveforms(continued)
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[33]
tWC ADDRESSR R/WR MATCH tPWE
tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATA OUTL tWDD VALID
tHD
tBHA tBDD
VALID
Figure 12. Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
Note 33. CEL = CER = LOW.
Document #: 38-06078 Rev. *B
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Switching Waveforms(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34] CELValid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CER Valid First:
ADDRESS L,R CER tPS CE L tBLC BUSY L tBHC ADDRESS MATCH
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[34] Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L tBHA ADDRESS MISMATCH
Note 34. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document #: 38-06078 Rev. *B
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Switching Waveforms(continued)
Figure 15. Interrupt Timing Diagrams Left Side Sets INTR :
ADDRESSL CE L R/W L INT R tINS [36] tWC WRITE 7FFF (FFFF for CY7C028V/38V) tHA[35]
Right Side Clears INT R :
ADDRESSR CE R tINR [36] R/WR OE R INTR
tRC READ 7FFF (FFFF for CY7C028V/38V)
Right Side Sets INT L:
tWC ADDRESSR CE R R/W R INT L tINS
[36]
WRITE 7FFE (FFFE for CY7C028V/38V) tHA[35]
Left Side Clears INT L:
ADDRESSR CE L tINR[36] R/W L OE L INT L
Notes 35. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 36. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 7FFE (FFFF for CY7C028V/38V)
Document #: 38-06078 Rev. *B
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Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L I/O9-I/O17 High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In Outputs I/O0-I/O8 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[37] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-14L 7FFF X X 7FFE INTL X X L[38] H[39] R/WR X X L X CER X L L X Right Port OER X L X X A0R-14R X 7FFF 7FFE X INTR L[39] H[38] X X
Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-I/O17 Left I/O0-I/O17 Right 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status
Notes 37. A0L-15L and A0R-15R,FFFF/FFFE for the CY7C028V/038V. 38. If BUSYR=L, then no change. 39. If BUSYL=L, then no change.
Document #: 38-06078 Rev. *B
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Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 15 Ordering Code CY7C027V-15AC CY7C027V-15AXC CY7C027VN-15AXC 20 25 CY7C027V-20AC CY7C027V-20AXC CY7C027V-25AC CY7C027V-25AXC CY7C027AV-25AXI Package Name A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial
64K x16 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 15 20 Ordering Code CY7C028V-15AC CY7C028V-15AXC CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC Package Name A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial
32K x18 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 15 20 25 Ordering Code CY7C037V-15AC CY7C037V-15AXC CY7C037V-20AC CY7C037AV-20AXC CY7C037V-25AC CY7C037V-25AXC Package Name A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Commercial
64K x18 3.3V Asynchronous Dual-Port SRAM
Speed (ns) 15 20 Ordering Code CY7C038V-15AC CY7C038V-15AXC CY7C038V-20AC CY7C038V-20AXC CY7C038V-20AI CY7C038V-20AXI 25 CY7C038V-25AC CY7C038V-25AXC Document #: 38-06078 Rev. *B Package Name A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Page 16 of 18
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Package Diagram
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
Document #: 38-06078 Rev. *B
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CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
Document History Page
Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 Rev. ** *A *B ECN No. 237626 259110 2623540 Orig. of Change YDT JHX VKN/PYRS Submission Date 6/30/04 See ECN 12/17/08 Description of Change Converted data sheet from old spec 38-00670 to conform with new data sheet. Removed cross information from features section Added Pb-Free packaging information. Added CY7C027VN, CY7C027AV and CY7C037AV parts Updated Ordering information table
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(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06078 Rev. *B
Revised December 09, 2008
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